Mehdi Nasrollahpour
Mehdi Nasrollahpour was born in Tehran, Iran. He received his B.S. degree from ShahidRajaee Teacher Training University, Tehran, Iran in 2015 and his master’s degree from San Jose State University, San Jose, California in 2017. From 2014 to 2015, he was a Research Assistant in the Microelectronic Circuits Laboratory (MECL) and joined Radio Frequency Integrated Circuits Laboratory (RFIC) and Analog Mixed-Signal Center from 2015. His research interests include analog mixed-signal and RF integrated circuits. He is currently doing research on time-based analog to digital converters and high frequency phase-locked loops for 5G and Radar applications. He serves as Analog IC Design engineer at Alpha and Omega semiconductor, Santa Clara, CA.
Mr. Nasrollahpour is the recipient of the 2017 Donald Beall-Rockwell Award for Engineering Accomplishment, IEEE 2017 NGCAS young professional award andthe best paper award for International Reliability Innovations Conference (IRIC) 2016.
2018 IEEE International Conference on RFID
10-12 April
Orlando, Florida
UPCOMING EVENTS
The 2018 IEEE 1st 5G World Forum (5GWF’18)
9-11 July
Santa Clara, CA
The International Symposium on Circuits and Systems (ISCAS) 2018
27-30 May
Florence, Italy
MY LATEST RESEARCH
RF to DC Converters
Analog to Digital Converters
RF energy is currently broadcasted from billions of radio transmitters around the world, including mobile telephones, handheld radios, mobile base stations, and television/ radio broadcast stations. The ability to harvest RF energy, from ambient or dedicated sources, enables wireless charging of low-power devices and has resulting benefits to product design, usability, and reliability. Battery-based systems can be trickled charged to eliminate battery replacement or extend the operating life of systems using disposable batteries. Battery-free devices can be designed to operate upon demand or when sufficient charge is accumulated. In both cases, these devices can be free of connectors, cables, and battery access panels, and have freedom of placement and mobility during charging and usage.
An Analog to Digital Converter is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude. Currently I am designing a time-based low power 5Bits 1GS/s Flash ADC in 65nm CMOS technology.
A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is "fed back" toward the input forming a loop.
When it comes to power dissipation and chip area, logic circuitry of a successive-approximation register A/D converter (SAR ADC), and to some extent, comparator, benefit from CMOS technology scaling. This is not always the case for the internal charge-redistribution D/A converter (DAC). The capacitor size of the DAC is a function of various parameters such as the smallest realizable capacitor, thermal noise (i.e. kT/C) and mismatch of the capacitors. Even today, in many implementations, the DAC is the largest block within the ADC’s layout. For low-power or area-critical applications, we do need to search for new DAC topologies. I am going to present new architecture to make the switching energy consumption and capacitor mismatches dependency as low as possible.
Digital to Analog Converters
Phase-Locked Loops
Low Noise Amplifiers
A low-noise amplifier (LNA) is an electronic amplifier that amplifies a very low-power signal without significantly degrading its signal-to-noise ratio. An amplifier increases the power of both the signal and the noise present at its input. LNAs are designed to minimize additional noise. Designers minimize noise by considering trade-offs that include impedance matching, choosing the amplifier technology (such as low-noise components) and selecting low-noise biasing conditions. • A very High FoM Bluetooth LNA Design in 45nm CMOS Technology is going to be designed.